中国电子ji术wang

设为首页 wang站地图 加入shoucang

 

guan键词:ECP5 FPGA SERDES ECP5-5G FPGAxi列

时间:2018-03-27 10:50:37       作者:Lattice       来源:中电wang

Lattice公司的ECP5/ECP5-5G FPGAxi列提供liao高xing能特xing如增强DSP架gou,高速SERDES和高速源同bu接口,采用40nmji术,shi得qi件非chang适he于量da高速和di成本的应用.qi件的查找biao(LUT)高达48K逻辑单元,zhi持duo达365个用户I/O,提供duo达156个18x18chengfaqi和各zhong并行I/O标zhun,采用可配置SRAM逻辑ji术,提供ji于LUT的逻辑,fen布式和嵌入式存chuqi,suo相huan(PLL),延迟suo定huan(DLL),zhi持预制源同buI/O,增强sysDSP slices和高dang配置,包括加密和双引dao功能.本wenjie绍liaoECP5和ECP5-5G FPGAxi列主yao特xing,LFE5UM/LFE5UM5G-85qi件简化框图以及ECP5 VIP 处理qi板主yao特xing,框图,路图和cai料清单.

The ECP5/ECP5-5G family of FPGA devices is optimized to deliver high performance features such as an enhanced DSP architecture, high speed SERDES (Serializer/Deserializer), and high speed source synchronous interfaces, in an economical FPGA fabric. This combination is achieved through advances in device architecture and the use of 40 nm technology making the devices suitable for high-volume, high-speed, and low-cost applications.

The ECP5/ECP5-5G device family covers look-up-table (LUT) capacity to 84K logic elements and supports up to 365 user I/Os. The ECP5/ECP5-5G device family also offers up to 156 18 x 18 multipliers and a wide range of parallel I/O standards.

The ECP5/ECP5-5G FPGA fabric is optimized high performance with low power and low cost in mind. The ECP5/ ECP5-5G devices utilize reconfigurable SRAM logic tech..

查看全wen

  • fen享到:

 

猜ni蟗u